This application is a divisional of U.S. application patent Ser. No, 11/297.237, now U.S. Pat. No. 7,476,923, filed Dec. 7, 2005, the entire disclosure of which is hereby incorporated by reference.
The invention relates to a semiconductor device and fabrication thereof, and in particular to a memory device and fabrication thereof.
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based on different objectives. The dynamic random access memory (DRAM) is an example of an important semiconductor device. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells.
Most DRAMs have one transistor and one capacitor in one DRAM cell. The memory capacity of the DRAM has reached 256 megabits. Therefore, under increasing integration the size of the memory cell and the transistor must shrink to yield DRAM with higher memory capacity and higher processing speed. A 3-D capacitor structure can itself reduce the occupied area in the semiconductor substrate, thus, the 3-D capacitor, such as a deep trench capacitor, is applied to the fabrication of the DRAM of 64 megabits and above. Traditional DRAM with a plane transistor covers larger areas of the semiconductor substrate and cannot satisfy the demand for high integration. Therefore, a vertical transistor which can save space is a trend in memory cell fabrication.
In general, when forming a memory device with vertical transistors and trench capacitors, formation of filling electrode (top electrode) is fabricated by deposition and etching. The etching back typically further comprises an over etching to completely remove the etched films. During the over etching step, divots may be formed on the filling electrode, and tip is formed on the interface between the filling electrode and a buried conductive layer to generate point discharge, thus, performance of the memory device is affected. In addition, the buried conductive layer is typically formed by filling a polysilicon layer into the region between the filling electrode and sidewalls of the trench. This method, however, is likely to generate seams. Since the buried conductive layer is a connection between the vertical transistor and the trench capacitor, seams in the buried conductive layer affect performance and reliability of the memory device.